1. Field of the Invention
The present invention generally relates to the field of electronic waveform sampling circuits, and more specifically to a power-efficient sample and hold circuit using bipolar transistors of single conductivity type.
2. Description of the Related Art
Sample and hold circuits charge a holding element, which is usually a capacitor, to the instantaneous amplitude of an analog input signal during a tracking or sampling interval, and then uncouple the signal from the capacitor during a holding interval. The sampled voltage which is held by the capacitor is typically applied to an analog-to-digital converter which produces a corresponding digital value which is stored in a random access memory of a waveform processing unit. A set of stored digital values obtained at increments of a sampled waveform constitutes a digital approximation of the analog signal, and can be analyzed or processed using a variety of known algorithms in accordance with a particular application.
FIG. 1 illustrates a basic prior art sample and hold circuit 10 including a diode bridge 12 such as described in U.S. Pat. No. 4,659,945, entitled "SAMPLING BRIDGE", issued Apr. 21, 1987 to A. Metz. The bridge 12 has a first bias current node N1 and a second bias current node N2. The anodes of diodes D1 and D3 are connected to the node N2, whereas the cathodes of diodes D2 and D4 are connected to the node N1. The cathodes of the diodes D1 and D3 are connected to the anodes of the diodes D2 and D4 respectively. An analog input voltage signal Vin for sampling is applied to the junction of the diodes D1 and D2, whereas an output signal Vout which appears at the junction of the diodes D3 and D4 is applied through an integrating resistor Rh to an integrating or holding capacitor Ch.
The diode bridge 12 further includes a diode D5 having a cathode connected to the node N2, and a diode D6 having an anode connected to the node N1. The anode of the diode D5 is connected to the cathode of the diode D6. A unity-gain replica of the output signal Vout is fed back through a buffer amplifier Al to the junction of the diodes D5 and D6 and designated as a bootstrap bias voltage Vbs. The diodes D5 and D6 are connected in anti-parallel relation to the diodes D1, D2, D3 and D4.
An NPN bipolar sampling transistor Q2 has a collector connected to the node N1 and an emitter connected to a constant current drain S1. A signal Vsample for selecting or commanding a tracking or sampling mode of operation is applied to the base of the transistor Q2. An NPN bipolar holding transistor Q1 has a collector connected to the node N2 and an emitter connected to the drain S1. A signal Vhold for selecting or commanding a holding mode of operation is applied to the base of the transistor Q1.
The drain S1 causes a predetermined constant bias current IBIAS to flow out of the bridge 12 through the node N1 and whichever transistor Q1 or Q2 is turned on into a voltage source VEE. A constant current source S2 is connected between a voltage source VCC, which produces a voltage higher than the voltage VEE, and the node N2. A constant current source S3, which is identical to the source S2, is connected between the voltage source VCC and the first node N1.
The sources S2 and S3 cause bias currents, each having a value of IBIAS/2, to flow into the bridge 12 through the nodes N2 and N1 respectively. In the illustrated topology in which the transistors Q1 and Q2 are of the NPN conductivity type, the sources S2 and S3 can be embodied by resistors (not shown).
The circuit 10 is operated in sampling mode by applying the sampling signal Vsample to the transistor Q2 and removing the holding signal Vhold from the transistor Q1. The transistor Q2 is turned on, thereby connecting the node N1 to the drain S1, whereas the transistor Q1 is turned off, thereby disconnecting the node N2 from the drain S1. The diodes D1, D2, D3 and D4 are forward biased, thereby coupling the signal Vin therethrough to the capacitor Ch which charges to the instantaneous value of the signal Vin to produce the signal Vout. The diodes D5 and D6 are reverse biased, and do not pass signal or bias current therethrough.
The bias current IBIAS flows out of the circuit 10 through the drain S1. Half of this current, IBIAS/2, flows through the source S2, node N2, diodes D1, D2, D3 and D4, node N1 and transistor Q2 to forward bias the diodes D1, D2, D3 and D4 and couple the input voltage signal Vin to the capacitor Ch. Another half IBIAS/2 of the bias current IBIAS flows through the source S3, node N1 and transistor Q2, and does not contribute to the sampling mode operation.
The circuit 10 is operated in holding mode by applying the holding signal Vhold to the transistor Q1 and removing the sampling signal Vsample from the transistor Q2. The transistor Q1 is turned on, thereby connecting the node N2 to the drain S1, whereas the transistor Q2 is turned off, thereby disconnecting the node N1 from the drain S1. The diodes D5 and D6 are forward biased by the bootstrap bias voltage Vbs, thereby causing the diodes D1, D2, D3 and D4 to be reverse biased and not pass signal or bias current therethrough, such that the signal Vin is uncoupled from the capacitor Ch.
The current IBIAS flows out of the circuit 10 through the drain S1 in holding mode as it does in sampling mode. Half of this current, IBIAS/2, flows through the source S3, node N1, diodes D5, and D6, node N2 and transistor Q1 to forward bias the diodes D5 and D6, reverse bias the diodes D1, D2, D3 and D4 and thereby uncouple the input voltage signal Vin from the capacitor Ch. Another half of this current, IBIAS/2, flows through the source S2, node N2 and transistor Q1, and does not contribute to the holding mode operation.
The diodes D5 and D6 must have a forward voltage drop which is larger than the forward voltage drop of the diodes D1, D2, D3 and D4 in order to cause the diodes D1, D2, D3 and D4 to be reverse biased when the diodes D5 and D6 are forward biased. Where a particular application must be implemented by diodes of a single type, the required effect can be produced by substituting two or more series diodes for each of the diodes D5 and D6, although not specifically illustrated.
The performance of the bridge 12 in following or tracking the input signal Vin can be improved by increasing the bias current flowing through the diodes D1, D2, D3 and D4 in the sampling mode. However, as described above, a current IBIAS/2, which is half of the total bias current IBIAS, flows around the bridge 12 from the source S3 and out through the node N1 in sampling mode rather than flowing through the diodes D1, D2, D3 and D4. This current IBIAS/2, which would improve the tracking performance of the bridge 12 if it flowed through the diodes D1, D2, D3 and D4 rather than bypassing the bridge 12, is wasted. The current IBIAS/2 which flows from the source S2 and out through the node N2 in holding mode is also wasted.
Another disadvantage of the circuit 10 in which the sources S2 and S3 are embodied as resistors is that since the voltage at the node N2 follows the input signal Vin, the current supplied into the bridge 12 through the sources S2 and S3 is modulated by the input voltage, thereby producing distortion in the signal Vout.
FIG. 2 illustrates an improvement to the circuit 10 in which all of the current IBIAS is caused to flow through the bridge 12 in both sampling and holding mode operation, in which like elements are designated by the same reference numerals used in FIG. 1. In a sample and hold circuit 16, the current sources S2 and S3 of the circuit 10 are replaced by a single constant bias current source S4 which causes the full bias current IBIAS to flow into the bridge 12. The circuit 16 includes a PNP bipolar transistor Q3 having an emitter connected to the source S4, a collector connected to the node N2 and a base connected to receive the sampling signal Vsample through an invertor IV1. A PNP bipolar transistor Q4 has an emitter connected to the source S4, a collector connected to the node N1 and a base connected to receive the holding signal Vhold through an invertor IV2.
In sampling mode, the transistor Q3 is turned on by the inverted sampling signal Vsample, thereby connecting the node N2 to the source S4. The transistor Q4 is turned off, thereby disconnecting the node N1 from the source S4. This causes the entire bias current IBIAS to flow from the source S4 through the transistor Q3, diodes D1, D2, D3 and D4 and transistor Q2 to the drain S1.
In holding mode, the transistor Q4 is turned on by the inverted holding signal Vhold, thereby connecting the node N1 to the source S4. The transistor Q3 is turned off, thereby disconnecting the node N2 from the source S4. This causes the entire bias current IBIAS to flow from the source S4 through the transistor Q4, diodes D5 and D6 and transistor Q1 to the drain S1.
Although the circuit 16 overcomes the drawbacks of the circuit 10 in that none of the bias current is wasted, the entire bias current is caused to flow through the bridge 12 in sampling mode and modulation of the source current by the input voltage is eliminated, it is not applicable to an integrated circuit topology in which all of the transistors must have the same conductivity type, either NPN or PNP. The circuit 16 is implemented by a complementary bipolar topology, with the transistors Q1 and Q2 being NPN conductivity type and the transistors Q3 and Q4 being PNP conductivity type.
Although it is theoretically possible to replace the transistors Q3 and Q4 with NPN transistors having their emitters and collectors reversed from the illustrated arrangement, the resulting circuit would be inoperative since the emitters of the NPN transistors would be connected to the bridge 12, the transistors would operate as emitter followers, and the voltage at the node N2 would follow the signal Vsample rather than the signal Vin.